The present invention relates to integrated circuit (IC) chip design and, more particularly, placement and insertion of wiring and silicon blockage on an IC chip.
Modern IC chip design typically involves the Very-large-scale integration (VLSI) process of arranging and inserting transistors, wiring paths and silicon blockages on a single chip. In a complex VLSI design environment where concurrent and hierarchical design is critical to meeting schedule, the ability to create and maintain robust wiring contracts becomes crucial. These wiring contracts are the cornerstone of enabling concurrent design and stitching multiple cell designs together (which share the same airspace) without creating shorts and overlaps.
One subset of this paradigm is the ability to insert front end-of-line (FEOL) cells at the top level of the design hierarchy (above child blocks) without overlapping cells or wire inside the child block. This especially becomes a necessity in the use of buffers (or signal repeaters) whose usage has escalated exponentially from technology to technology because of ever increasing circuit densities and the fact that wire performance has been unable to keep up with increasing circuit performance. In a case where the chip top level floorplan will utilize a million or so buffers, it becomes critical that the designer can place these buffers where they are needed, especially in a floorplan dominated by large sub-blocks (or units). It is also just as important to keep these buffers at the top level instead of trying to insert chip level signals into child blocks, which would then require changes in the netlist of those child blocks. Being able to control buffer insertion at one's own level of hierarchy prevents costly updates of Verilog/VHDL and provides more independence of the physical design from the logic design. Historically, inserting buffers over child blocks has been done by creating silicon and wire ‘cut-outs’ in the child block that can utilized by the parent level. In previous designs, these cut-outs were rigid and tedious to implement.